发明名称 SAMPLING CLOCK CONTROL METHOD OF DIVERSITY RECEIVER AND DIVERSITY RECEIVER
摘要 PROBLEM TO BE SOLVED: To provide a clock control method of a diversity receiver capable of reproducing stable clock with little jitter, fewer phase errors or the like even if the quality of a reception signal is in a low state, and also to provide a diversity receiver. SOLUTION: The diversity receiver for compositing or selecting reception signals received by a plurality of antennas 21 to 25 composites the reception signals at a ratio based on the quality of reception signals of respective branches (11), and controls a sampling clock of the diversity receiver on the basis of a composited result. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006325077(A) 申请公布日期 2006.11.30
申请号 JP20050147907 申请日期 2005.05.20
申请人 HITACHI KOKUSAI ELECTRIC INC;NIPPON HOSO KYOKAI <NHK> 发明人 NAKADA TATSUHIRO;TADA YASUTOSHI;KIMURA SATOSHI;TSUCHIDA KENICHI;TAKADA MASAYUKI;ITO YASUHIRO;NAKAMURA NAOYOSHI
分类号 H04B7/08;H04B7/26;H04J11/00 主分类号 H04B7/08
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