| 摘要 |
A clock driver circuit has a plurality of driver circuits 20, 30 connected in parallel with each other, and a control circuit 40 for stopping the operation of a part of the plurality of driver circuits for a given period of time, based on at least one of a rise and a fall of an input signal. From the rising/falling edges of the input signal until a predetermined time lapses, all of the driver circuits 20, 30 operate in parallel concurrently to thereby exhibit a high driving capability. Subsequently, the part of the drivers stops the operation during a transient period of an output waveform to thereby prevent the overshoot/undershoot. Therefore, overshoot/undershoot is prevented while a higher driving capability is realized.
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