发明名称 PATTERN LAYOUT IN INTEGRATED CIRCUIT, PHOTOMASK, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND DATA CREATING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To increase resolution in a pattern even in an end portion of a line-and-space pattern, and to suppress decrease in a lithographic margin or increase in a CAD processing time. <P>SOLUTION: The photomask having a pattern to be transferred into an integrated circuit by exposure includes a first device pattern 10 where lines and spaces are alternately arranged at a fixed pitch of a predetermined spacing in one direction, a second device pattern 20 laid as separated from the end of the first device pattern 10 in the arrangement direction and having a width as three times or more in an odd number as the fixed pitch, a dummy pattern 30 laid between the first and second device patterns 10, 20 and having lines and spaces alternately arranged at a fixed pitch giving no influence on circuit operation, and auxiliary pattern 21a, 22a laid in the second device pattern 20 at a fixed pitch and not resolved by exposure. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006293081(A) 申请公布日期 2006.10.26
申请号 JP20050114752 申请日期 2005.04.12
申请人 TOSHIBA CORP 发明人 INOMOTO MINORU;KAI YASUNOBU;MASHITA HIROMITSU;HASHIMOTO KOJI;FUJISAWA TADAHITO
分类号 G03F1/36;G03F1/68;G03F1/70;H01L21/027;H01L21/28;H01L21/3205;H01L21/768;H01L21/82;H01L23/52;H01L23/522 主分类号 G03F1/36
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