发明名称 ON-CHIP TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide an on-chip test circuit which can output the measurement result of internal delay time of an access time or the like of a semiconductor memory apparatus to the outside and does not require a test function having high performance for the external tester. SOLUTION: The circuit is provided with a reference clock generating circuit 11 which is operated by power source voltage Vct for test being different from a circuit part 20 to be measured of the semiconductor memory apparatus 1 and which can adjust an oscillation period of a reference clock CLK generated by a voltage value of the power source voltage Vct for test, a reference clock output circuit 12 outputting a reference clock signal S2 oscillating with a period of fixed number times of a period of the reference clock CLK or more, and a timing discriminating circuit 15 in which at the time of a test mode where the circuit part 20 to be measured is operated synchronizing with the reference clock CLK, the prescribed internal delay signal DTj outputted from the circuit part 20 to be measured is compared with the prescribed signal level Ej with a discrimination timing prescribed by the reference clock CLK, the compared result S5 is held so as to be outputted to the outside. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006244556(A) 申请公布日期 2006.09.14
申请号 JP20050055909 申请日期 2005.03.01
申请人 SHARP CORP 发明人 MORIKAWA YOSHINAO
分类号 G11C29/12;G01R31/28;H01L21/822;H01L27/04 主分类号 G11C29/12
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