| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which carries out optimum locking action for a wide input frequency range and is advantageous to reduce jitter. <P>SOLUTION: The PLL circuit comprises a phase comparator 11, a variable charge pump circuit 12, a variable low-pass filter 13, a voltage-controlled oscillation circuit 14, a variable divider 15, and a frequency determination circuit 16. When the frequency determination circuit 16 determines a change of the frequency of an input signal, at least two values out of the current value of the current signal output from the variable charge pump circuit 12, a filtering characteristic value of the variable low-pass filter 13, and the dividing ratio of the variable divider 15, are changed to respective prescribed values so that the band frequency of the phase locked loop can be changed while the damping factor of the phase locked loop is kept constant. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
