| 摘要 |
PROBLEM TO BE SOLVED: To provide a high level synthesis apparatus, an automatic high level synthesis method and a high level synthesis program that automatically convert assertion information described in an operation description to assertion information describable as a register transfer level (RTL) description. SOLUTION: The high level synthesis apparatus comprises a C/DFG extraction part 101 for extracting from an operation description a control dataflow graph including first assertion information for verifying circuit operations described in the operation description, an assertion extraction part 102 for extracting the first assertion information from the control dataflow graph, a conversion part 110 for converting the first assertion information to second assertion information describable as a register transfer level description according to scheduling results and allocation results of a circuit control dataflow graph remaining by the extraction of the first assertion information from the control dataflow graph, and an RTL creation part 106 for creating an RTL assertion description described as a register transfer level description according to the converted second assertion information. COPYRIGHT: (C)2006,JPO&NCIPI
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