发明名称 |
3-D column select circuit layout in semiconductor memory devices |
摘要 |
A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.
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申请公布号 |
US2006138465(A1) |
申请公布日期 |
2006.06.29 |
申请号 |
US20050206437 |
申请日期 |
2005.08.18 |
申请人 |
CHOI BYUNG-GIL;SUH YOUNG-HO |
发明人 |
CHOI BYUNG-GIL;SUH YOUNG-HO |
分类号 |
H01L27/10;H01L29/739;H01L29/76 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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