| 摘要 |
A method according to one embodiment may include transmitting a plurality of packets through control pipeline circuitry of an integrated circuit of a switch. The control pipeline circuitry may be capable of making a plurality of memory requests to memory of the switch in response to the plurality of packets. The method may further comprise staggering the plurality of memory requests so that each of the plurality of memory requests occurs during a different one of a plurality of time slots. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
|
