HIGH SPEED AND LOW POWER SRAM MACRO ARCHITECTURE AND METHOD

摘要

Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or more controllable source transistors. By way of example the circuit has at least one source transistor (e.g., power, ground, or both power and ground) for selectively supplying power to a stage within an integrated circuit device. A means for modulating the state of the source transistor operates in response to changes in the operating mode of the integrated circuit to turn on the source transistor prior to turning on the logic transistors, and/or to turn off the source transistor after turning off the logic transistors. In one aspect, the delay prior to turning off the logic transistors can be sufficiently extended to reduce power consumption arising from unnecessarily turning on and off the source transistors for short periods.