发明名称 |
Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section |
摘要 |
An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the "read" data path for each section such that the number of delays in the address/clock path plus the number of delays in the "read" data path is substantially constant.
|
申请公布号 |
US7039822(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20030375575 |
申请日期 |
2003.02.27 |
申请人 |
PROMOS TECHNOLOGIES INC. |
发明人 |
FAUE JON ALLAN;MEADOWS HAROLD BRETT |
分类号 |
G06F13/42;G06F17/50;G11C7/10;G11C11/408;G11C11/4097;H04L7/00 |
主分类号 |
G06F13/42 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|