| 摘要 |
There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal "A" is in a "L" level and a signal PL entered from the outside of the voltage level control circuit becomes "H" level, a latch signal La outputted from a latch ( 11 ) becomes "H" level, whereby NFETs ( 14, 17, 24 ) turn ON. A voltage dividing circuit comprising resistances ( 12, 13 ) and current mirror differential amplifiers ( 20, 27 ) are placed in active states to output "H" as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref 2, a voltage V 2 becomes "H", whereby the signal A becomes "L". After the signal A become "L", the latch ( 11 ) is made through. At this time, the signal PL is "L", the latch signal La outputted from the latch ( 11 ) becomes "L", whereby the NFETs ( 14, 7, 24 ) turn OFF. As described here, the NFETs ( 14, 7, 24 ) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
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