发明名称 |
Method for making a semiconductor device with reduced spacing |
摘要 |
Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.
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申请公布号 |
US2005287810(A1) |
申请公布日期 |
2005.12.29 |
申请号 |
US20040878839 |
申请日期 |
2004.06.28 |
申请人 |
LI CHI NAN B;HONG CHEONG M;SINGH RANA P |
发明人 |
LI CHI NAN B.;HONG CHEONG M.;SINGH RANA P. |
分类号 |
H01L21/302;H01L21/311;H01L21/8247;H01L27/115;(IPC1-7):H01L21/311 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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