| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DRAM that enables high-speed operation and low power consumption. <P>SOLUTION: A couple of precharge MOSFETs are provided which supply precharge voltages to a couple of input and output nodes of a CMOS sense amplifier, the couple of input and output nodes are connected to a complementary bit line couple through a select switch MOSFET, and a 1st equalizing MOSFET which performs equalization is provided between the complementary paired bit lines, and a memory cell is provided between word lines which cross one of the complementary paired bit lines, gate insulating films of the select switch MOSFET and 1st equalizing MOSFET are formed with a 1st film thickness, and a gate insulating film of the precharge MOSFET is formed with a 2nd film thickness thinner than the 1st film thickness. A precharge signal corresponding to a source voltage is supplied to the precharge MOSFET and an equalization signal and a selection signal corresponding to boosted voltages are supplied to the 1st equalizing MOSFET and a selection switch MOSFET. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
