| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a processor capable of reducing power consumption in a peak time. <P>SOLUTION: This processor includes an instruction decode part 11 decoding a fetched instruction and a plurality of computing units from 12-1 to 12-4 executing computing according to a decode result by the instruction decode part 11. The instruction decode part 11 retracts dependent data to a register to use them when fetched instructions are parallel instructions including a plurality of instructions and there is dependency between a plurality of instructions. In this way, the parallel instructions are sequentially operated by a part of the computing units among the plurality of computing units from 12-1 to 12-4. Therefore, a part of the computing units are not required to be operated, and consequently, power consumption in the peak time can be lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
