| 摘要 |
A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output. A write select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage. Each stage of the write select shift register has an output connected to a respective one of the write select inputs of the write select multiplexer. The write select shift register is clocked with the write clock signal. A read select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage. Each stage of the read shift register has an output connected to a respective one of the read select inputs of the read select multiplexer. The read select shift register is clocked with the read clock signal. A reset circuit for initializes each shift register with a bit pattern that contains only one high value, the bit patterns in the shift registers having a constant relative offset. In operation, a clocked data input stream synchronized with the clock of the first clock domain is applied to the data inputs of the registers and a clocked data output stream synchronized with the clock of the second clock domain is taken from the data outputs of the registers.
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