发明名称
摘要 In a phase locked loop (PLL) circuit having a function of automatically adjusting the free-running frequency of a voltage controlled oscillator (VCO), the number of pulses of a pulse signal output from the VCO in a period in which a comparison signal output from a phase comparator is at a predetermined level is counted, and a microcomputer updates digital data based on the counted value. The digital data is converted into an analog signal by a digital-to-analog converter. A combiner combines the analog signal with a signal obtained by smoothing the comparison signal of the phase comparator by a low-pass filter so as to generate a frequency control signal of the VCO.
申请公布号 JP3674850(B2) 申请公布日期 2005.07.27
申请号 JP20010376964 申请日期 2001.12.11
申请人 发明人
分类号 G09G3/20;H03L7/085;H03L7/10;H03L7/113;H03L7/189 主分类号 G09G3/20
代理机构 代理人
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