发明名称 Data processor and data processing method reduced in power consumption during memory access
摘要 When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.
申请公布号 US6918002(B2) 申请公布日期 2005.07.12
申请号 US20020053545 申请日期 2002.01.24
申请人 RENESAS TECHNOLOGY CORP. 发明人 KUMAKI SATOSHI;MATSUMURA TETSUYA;SEGAWA HIROSHI;HANAMI ATSUO;MOSNEAGA VASILE
分类号 G06F1/26;G06F1/32;G06F12/00;G06F12/04;G06F13/42;(IPC1-7):G06F12/00 主分类号 G06F1/26
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