| 摘要 |
A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.
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