发明名称 Delay circuit, ferroelectric memory device and electronic equipment
摘要 A delay circuit generates an output signal by delaying an input signal, and includes a ferroelectric capacitor having a first end and a second end, a means for inverting a polarization of the ferroelectric capacitor by producing an electric potential difference between the first end and the second end based on an electric potential of the input signal and a generation means for generating the output signal by delaying the input signal based on a change in an electric potential of the second end caused by the polarization inversion.
申请公布号 US2005128859(A1) 申请公布日期 2005.06.16
申请号 US20040997820 申请日期 2004.11.24
申请人 WATANABE KENYA 发明人 WATANABE KENYA
分类号 G11C11/22;G11C7/10;G11C7/22;G11C8/02;G11C11/409;G11C29/02;G11C29/50;H03K5/13;H03K5/14;(IPC1-7):G11C8/02 主分类号 G11C11/22
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