| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a compact packet processor which cuts down the number of reconfigurable devices used. <P>SOLUTION: The packet processor 1 is composed of a serial connection of an input buffer 13, a plurality of reconfigurable devices 11, 12, and an output buffer 14, and of fed-back reconfigurable devices 11, 12. A processing unit constituting means 132 of the input buffer 13 outputs a packet flow 112 per process unit composed of free areas and a process result storing area added to one or a plurality of packet units. The reconfigurable device 11 executes a process A to form a process C by reconfiguration. The reconfigurable device 12 executes a process B to form a process D by reconfiguration. When a process of a specified number of feedback times is completed, the output buffer 14 outputs a packet flow 115 to the outside. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
