| 摘要 |
<p>A scan control circuit sends the first shift clock to a scan connection configuration circuit and to a memory array from the last register to the first register sequentially. By doing so, data is first copied in parallel from the first element of the last register of the memory array to the second storage element of the scan connection configuration circuit, and shift data is output externally from the second storage element of the least-significant bit of the scan connection configuration circuit to the shift register output terminal. Next, data is sequentially copied in parallel from the first storage elements of a high-order register in the memory array to the first storage elements of a low-order register. For the first register, data in the second storage elements except the most-significant bit of the scan connection configuration circuit is copied in parallel to the first storage elements except the most-significant bit. Last, shift data received externally at the shift register input terminal is copied by inputting a second shift clock into the first storage element of the most-significant bit of the first register. This processing is repeated until all data held in the memory array at scan start time is output externally from the shift register output terminal.</p> |
