发明名称 Semiconductor memory device for storing multivalued data
摘要 In the operation of writing the second page, the control circuit precharges the bit line in verifying data "2" in the memory cell when the DDC has data "1" in it after the data cache is set and does not precharge the bit line when the DDC has data "0" in it. As a result, when data "2" has been written into the memory cell, the bit line is at the intermediate potential, which raises the threshold voltage of the memory cell a little.
申请公布号 US2005047217(A1) 申请公布日期 2005.03.03
申请号 US20030689868 申请日期 2003.10.20
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIBATA NOBORU;TANAKA TOMOHARU
分类号 G11C16/10;G11C11/56;G11C16/04;G11C16/12;(IPC1-7):G11C5/00 主分类号 G11C16/10
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