发明名称 |
METHOD OF MANUFACTURING DIFFUSED WAFER |
摘要 |
PROBLEM TO BE SOLVED: To significantly lower the fraction defective of the withstand voltage of a semiconductor device using a power MOS transistor by manufacturing a diffused wafer containing Fe at a concentration of≤100×10<SP>12</SP>atoms/cm<SP>3</SP>by using a heat-treating member containing Fe at a concentration of≤0.5 ppm. SOLUTION: In a method of manufacturing a diffused wafer obtained by diffusing an impurity in a wafer and containing Fe at a concentration of≤100×10<SP>12</SP>atoms/cm<SP>3</SP>, the wafer is heat-treated at a high temperature by means of the heat-treating member containing Fe at a concentration of≤0.5 ppm. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2005019458(A) |
申请公布日期 |
2005.01.20 |
申请号 |
JP20030178363 |
申请日期 |
2003.06.23 |
申请人 |
TOSHIBA CERAMICS CO LTD;TOSHIBA CORP |
发明人 |
KIRYU TAKAHIRO;SUDO YOSHIKATSU;KANEKO TADAYOSHI;SAKATA NAOYOSHI |
分类号 |
H01L21/22;(IPC1-7):H01L21/22 |
主分类号 |
H01L21/22 |
代理机构 |
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主权项 |
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地址 |
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