发明名称 |
Low jitter external clocking |
摘要 |
A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
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申请公布号 |
US6798265(B2) |
申请公布日期 |
2004.09.28 |
申请号 |
US20020132599 |
申请日期 |
2002.04.25 |
申请人 |
INTEL CORPORATION |
发明人 |
NAIR RAJENDRAN;DERMER GREGORY E.;MOONEY STEPHEN R.;BORKAR NITIN Y. |
分类号 |
G06F1/10;H03K5/24;(IPC1-7):G06F1/04;H03K3/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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