| 摘要 |
PROBLEM TO BE SOLVED: To provide an address buffer having (N/2) stages. SOLUTION: The address buffer used for a semiconductor device having N (N is a natural number) pieces of additive latencies is provided with serially connected (N/2) flip-flops, and an address control circuit for generating an address enable signal in response to a clock signal and a command signal, and each of the (N/2) pieces of flip-flops is clocked by the address enable signal to sequentially latch external addresses. The address buffer used for the semiconductor device having the N pieces of additive latencies has (N/2) stages and has the same functions as an N stage address buffer. COPYRIGHT: (C)2004,JPO&NCIPI |
