| 摘要 |
PROBLEM TO BE SOLVED: To improve the lack of an operating margin and an operation failure caused by signal wiring laid between circuit blocks without replacing a mask after a chip is inspected. SOLUTION: A logic circuit block 11 and a memory circuit block 12 are provided to a semiconductor chip 10, and a timing control circuit block 13 controlling the transmission timing of signals is provided to an interconnect line between the circuit blocks 11 and 12. The timing control circuit 30 is composed of a delay element block 31 equipped with a plurality of delay elements A, B, and C giving different amounts of delay to inter-block signals DA1, a counter circuit block 32 which receives timing regulating/controlling signals CNT from the timing control circuit block 13, and a fuse circuit block 33 which is fused on the basis of fuse information signals FO possessed by the counter circuit block 32 and has the substantial same function with the counter circuit block 32. COPYRIGHT: (C)2004,JPO&NCIPI
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