发明名称 |
Memory module, e.g. for use in computer systems, with number of integrated memory components has separate access control circuit that generates column and row addresses from memory access addresses |
摘要 |
<p>The device has a carrier substrate (50) with connections (40) for feeding address and command signals, integrated memory components (10-18;20-28) on the substrate and a separate access control circuit (30) on the substrate with inputs connected to the connections for feeding address and command signals and outputs to the integrated memory components. The access control circuit generates column and row addresses (CADR,RADR) from memory access addresses.</p> |
申请公布号 |
DE10305837(A1) |
申请公布日期 |
2004.09.02 |
申请号 |
DE2003105837 |
申请日期 |
2003.02.12 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
JAKOBS, ANDREAS |
分类号 |
G11C11/408;(IPC1-7):G11C11/408 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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