| 摘要 |
The circuit has a defined voltage (VRef) applied to a memory cell (SZelle) read output via which a state of charge current (I1) flows. A regulating transistor (RT1) source-drain path is connected to the read output. A differential amplifier (DV1) output is connected to the regulating transistor gate and the regulating transistor gate voltage can be controlled by the differential amplifier so that the defined voltage is applied at the read output. Independent claims are also included for the following: a read-out circuit for determining state of charge of non-volatile semiconducting memory cells, a matrix arrangement of non-volatile semiconducting memory cells and an EEPROM, EAROM or Flash-EPROM memory component with a number of non-volatile semiconducting memory cells. |
