发明名称 |
Intelligent interleaving scheme for multibank memory |
摘要 |
A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so that the same memory bank is not used for back-to-back packet reads. The last memory bank write is determined for each output queue. This write information is used in combination with look ahead packet read information for a group of packets from the next output queue scheduled to read packets from memory. The scheduler uses all this information to avoid any back-to-back packet read, write, or read/write accesses to the same memory bank. This intelligent packet interleaving scheme preserves memory bus bandwidth normally wasted accessing the same memory banks.
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申请公布号 |
US6745277(B1) |
申请公布日期 |
2004.06.01 |
申请号 |
US20000679266 |
申请日期 |
2000.10.04 |
申请人 |
FORCE10 NETWORKS, INC. |
发明人 |
LEE EUGENE;SIKDAR SOMSUBHRA |
分类号 |
G06F12/00;G06F12/06;G06F13/16;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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