| 摘要 |
A multiply accumulator with an optimum timing performs multiplications and additions at the same time by commonly accumulating partial products and addends. First of all, timings of bits of the partial products and timings of bits of the addend are defined. A sum delay parameter and a carry delay parameter associated with adders to be used for constructing the multiply accumulator are retrieved from a circuit design standard cell library. Based on the timings of bits of the partial products and the addend, and the sum delay and carry delay parameters, the bits of the partial products and the addend are assigned to input terminals of the adders, and the input and output terminals of the adders are interconnected by using a three dimensional reduction method. Finally, a net list representative of the multiply accumulator with the optimum timing is output.
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