发明名称 Minimization and linearization of ESD parasitic capacitance in integrated circuits
摘要 An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive sub-circuit 302, each sub-circuit including an MOS transistor. The circuit comprises a direct connection between the I/O pad 303 and the drain 321 of the drive sub-circuit MOS transistor 306, and further a forward diode 360 inserted between the I/O pad 303 and the drain 311 of the discharge sub-circuit MOS transistor 305 to isolate the junction capacitance of the discharge sub-circuit MOS transistor, whereby electrical noise coupling to the substrate is reduced, RF/analog input signals are improved, and leakage at the I/O pad is reduced.
申请公布号 US6690066(B1) 申请公布日期 2004.02.10
申请号 US20020274163 申请日期 2002.10.18
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 LIN HENG-CHIH;DUVVURY CHARVAKA;HAROUN BAHER
分类号 H01L23/62;H01L27/02;(IPC1-7):H01L23/62 主分类号 H01L23/62
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