发明名称 |
Schaltung mit gemischten Signalen und Geräte integrierter Schaltungen |
摘要 |
In mixed-signal circuitry signal control circuitry (12) is interposed between digital circuitry (10) and analog circuitry (14). The signal control circuitry comprises a plurality of individual clocked signals (L1-Ln), each connected for receiving one or more first digital signals (T1-Tn) and also connected for receiving a clock signal (CLK) . Each clocked circuit derives from the received first digital signal(s) at least one second digital signal (TCK1-TCKn) and applies that derived second digital signal to an analog-circuitry input at a time determined by the received clock signal. The signal control circuitry also comprises clock distribution circuitry including a plurality of block buffer circuits (B1-Bn) connected in common for receiving a basic timing signal (BCLK). Each clock buffer circuit derives from the basic timing signal such a clock signal (CLK1-CLKn) for application to one or more corresponding ones of the said clocked circuits (L1-Ln). <IMAGE> |
申请公布号 |
DE69909523(T2) |
申请公布日期 |
2003.12.24 |
申请号 |
DE1999609523T |
申请日期 |
1999.01.06 |
申请人 |
FUJITSU MICROELECTRONICS EUROPE GMBH |
发明人 |
DEDIC, IAN JUSO;SCHOFIELD, WILLIAM GEORGE JOHN |
分类号 |
H01L21/822;G06F1/04;G06F1/10;H01L27/04;H01L27/092;H01L27/12;H03M1/08;H03M1/36;H03M1/74 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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