发明名称 Method and apparatus for virtual register renaming to implement an out-of-order processor
摘要 A computing device including a logical register file having a specified number of logical registers, each logical register storing an architected operand, and a physical register file having a specified number of physical registers, each physical register storing either a speculative operand or a architected operand. A plurality of virtual register numbers is provided that is greater than the number of logical registers plus physical registers. Each virtual register number is assigned to provide a direct index into the physical register file, with additional bits to store other information. A processor processes an instruction by using virtual numbers to directly index the physical register file to obtain any necessary input operand, or to determine that the operand is available only from the logical register file. Accordingly, the physical register file contains some speculative operands and some architected operands while the logical file only contains architected operands.
申请公布号 US2003217249(A1) 申请公布日期 2003.11.20
申请号 US20020151605 申请日期 2002.05.20
申请人 THE REGENTS OF THE UNIVERSITY OF MICHIGAN 发明人 POSTIFF MATTHEW A.;MUDGE TREVOR;GREENE DAVID;RAASCH STEVEN
分类号 G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/38
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