发明名称 |
Secure EEPROM memory comprising an error correction circuit |
摘要 |
An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.
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申请公布号 |
US2003126513(A1) |
申请公布日期 |
2003.07.03 |
申请号 |
US20020317005 |
申请日期 |
2002.12.11 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
WUIDART SYLVIE |
分类号 |
G11C16/02;G06F11/08;G06F11/10;G11C16/06;G11C16/22;G11C29/42;(IPC1-7):H04B1/74 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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