| 摘要 |
A semiconductor memory device that can increase only the data transfer rate while the clock speed and the internal operation speed of a DDR-DRAM remain unchanged, comprising two DDR-DRAMs, in one package, commonly connected to data input/output lines to form an integrated semiconductor memory device. The semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRMAs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.
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