METHOD FOR FABRICATING SEMICONDUCTOR TRANSISTOR INCLUDING SILICIDE PATTERN

摘要

PURPOSE: A method for fabricating a semiconductor transistor including a silicide pattern is provided to minimize disconnection or agglomeration of a gate silicide pattern by forming a spacer with an upper surface lower than a gate conductive layer pattern. CONSTITUTION: The gate conductive layer pattern(120) is formed on a semiconductor substrate(100). A lower insulation layer, and intermediate insulation layer and an upper insulation layer are sequentially stacked on the front surface of the semiconductor substrate including the gate conductive layer pattern. The upper insulation layer is anisotropically etched to form an upper spacer exposing the upper surface of the intermediate insulation layer. The exposed intermediate insulation layer is etched to form an L-shaped intermediate spacer(145) having an upper surface lower than the gate conductive layer pattern. The upper spacer is removed while the lower insulation layer is etched so that a lower spacer is formed which exposes the upper surface and upper sidewall of the gate conductive layer pattern and the semiconductor substrate at the side of the intermediate spacer. Gate silicide and junction region silicide are respectively formed on the gate conductive layer pattern and the exposed surface of the semiconductor substrate.