发明名称 PLL circuit
摘要 A PLL circuit having a wide oscillation frequency range, and capable of reducing a jitter. The PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal. An oscillator generates an oscillation frequency signal having an oscillation frequency according to a control signal having a current corresponding to the phase difference signal. A detection circuit generates a detection signal by detecting the current of the control signal. A signal generation circuit generates a signal for changing the oscillation frequency of the oscillator such that the current of the control signal is within a predetermined range in accordance with the detection signal.
申请公布号 US2003076140(A1) 申请公布日期 2003.04.24
申请号 US20020106257 申请日期 2002.03.27
申请人 FUJITSU LIMITED 发明人 ASANO SHIGETAKA
分类号 H03L7/089;H03L7/093;H03L7/095;H03L7/10;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03L7/089
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