| 摘要 |
PROBLEM TO BE SOLVED: To provide new fetch branch architecture for reducing branch penalty without branch prediction. SOLUTION: In lieu of the branch prediction, a merged fetch-branch unit operates in parallel with a decode unit in a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked as regular instructions, the branch instruction is marked as such and any instructions following the branch are marked as sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
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