| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock synchronous type data transfer processing device preventing surely racing with simple circuit constitution. SOLUTION: In a transfer circuit which is constituted of a plurality of latch circuits (RDa-RDc) being cascade-connected, in which continued latch circuits are made complementally a latch state and a transparent state, and which transfers data/signal responding to a clock signal, clock control circuits (CTLa- CTLc) controlling operation of these latch circuits detect that the next stage latch circuit is made a latch state and permit transfer of signal/data of a corresponding latch circuit, and transfer the data/signal conforming to the corresponding clock signal. When the next stage latch circuit is in a transparent state, it can be prevented that the data/signal is transferred, the data/signal can be precisely transferred. |
