| 摘要 |
To reduce test time, test circuit configuration in which the parallel execution of a test of an I/O device and a test of an internal circuit is enabled in a semiconductor integrated circuit provided with scan test functions and a test method are provided. A test is made by a test circuit having an operational mode composed of a scan path used for observing a value of a signal fetched from an external terminal by an input buffer and setting the output value of an output buffer and a scan path used for setting a value of a signal applied to the internal circuit and observing a value of a signal output from the internal circuit in addition to a normal boundary scan operational mode. Hereby, as the test of the I/O device and the test of the internal circuit can be executed in parallel, test time can be reduced.
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