发明名称 METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To solve the problem in conventional LVS verification such as that it can be judged whether a well is fixed to potential as per a circuit diagram or not but it cannot be judged whether proper setting of potential fixation is set to the individual devices within the well or not. SOLUTION: The approximation formula of potential fixing strength is made by defining the potential regulation of the well which occurs when the device operates as potential fixing strength and modeling the action by the transition property of an RC series circuit. Then the in-plane distribution of the potential fixing strength on the well is abstracted based on the approximation formula. Then, the device arranged under the potential fixing strength under a preset threshold is abstracted as an error.
申请公布号 JP2002343866(A) 申请公布日期 2002.11.29
申请号 JP20010147941 申请日期 2001.05.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 YONETANI HIDEKI
分类号 G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F17/50
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