| 摘要 |
PURPOSE: A SRAM cell array is provided, which can improve an operation characteristics and a reliability of a device by minimizing a voltage increase at a VSS node by dispersing uniformly a current flowing in cells selected at the same time. CONSTITUTION: N type well regions(52) are formed in a P type well region(51), and are used as Vcc supply lines. The first and the second active region are formed in the N type well region. The third, the fourth, the fifth and the sixth active region are formed in the P type well region, and are located above and below a Y direction one by one in correspondence to the first and the second active region. A Vss line is connected to a part passing a separation region between the first and the second active region along the Y direction and is connected to a part crossing the above part along a X direction on the third and the fourth active region and on the fifth and the sixth active region. A Vcc interconnect connects a Vcc pickup region formed in the N type well region and the first and the second active region. Conductive lines(62a,62b,62c,62d) form four unit cells on the active regions. And a bit line(60) and /bit lines(61) pass the unit cell along the Y direction without being overlapped with the Vss line, and word lines(59a,59b) pass the third and the fourth active region and the fifth and the sixth active region along the X direction without being overlapped with the Vss line.
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