| 摘要 |
<p>An integrated circuit (2) is provided with a serial test scan chain (10) for testing proper operation. Asynchronous reset signal operation may be tested by using a reset signal generating scan chain cell (20) that is adapted such that a reset signal value held within a latch (14) of that cell is asynchronously gated to be applied to the circuit portion (8) under test b y the scan enable signal. The latches (12) within the circuit portion under test that are forced to predetermine values by the correct operation of the reset may be preloaded with opposite sense values prior to the reset test.</p> |
