发明名称 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To obtain a method for fabricating a high performance high integration semiconductor device inexpensively in which parasitic capacitance is reduced by reducing the effective dielectric constant between lines and between interconnection layers and the fabrication process is reduced as compared with prior art. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a multilevel metallization by laying a plurality of interconnection layers on a substrate while insulating between lines and between interconnection layers with an insulation film. The method further comprises steps for forming at least a part of the multilevel metallization (e.g. a first metallization 34, a second metallization 39) using an insulation film (a second insulation film 23, a third insulation film 42) at least a part of which is removed selectively with respect to the interconnection material, dicing a chip 3 from the substrate following to formation of the multilevel metallization to expose the cross-section of the insulation film, and removing the second insulation film 23 and the third insulation film 42 selectively from the cross-section to make cavities 81 and 82 exposing the first metallization 34 and the second metallization 39.
申请公布号 JP2002184859(A) 申请公布日期 2002.06.28
申请号 JP20000381271 申请日期 2000.12.15
申请人 SONY CORP 发明人 MIYATA KOJI
分类号 H01L21/302;H01L21/3065;H01L21/3205;H01L21/768;H01L23/52;H01L23/522;(IPC1-7):H01L21/768;H01L21/306;H01L21/320 主分类号 H01L21/302
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