Synchronous data transmission process

摘要

Two devices (D1,D2) may transmit data using clock thread (CK) and at least a data thread (DT). The clock thread is maintained by default to a logical value A that may be converted to an electric potential representing a logical value B inverse of A. The two devices may convert B to the CK at the time of data transmission. A target device to which the data is sent does not loose the CK since it does not read the data. The data-sending device maintains it until the CK is released by the device to which data is targeted. Independent claims are included for: (a) a data transmission-reception device (b) a synchronous data transmission device (c) an interface circuit for data transmission in master-slave configuration