发明名称 |
Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts |
摘要 |
A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.
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申请公布号 |
US6374344(B1) |
申请公布日期 |
2002.04.16 |
申请号 |
US19980200248 |
申请日期 |
1998.11.25 |
申请人 |
COMPAQ INFORMATION TECHNOLOGIES GROUP L.P. (CITG) |
发明人 |
WEBB, JR. DAVID ARTHUR JAMES;KELLER JAMES B.;MEYER DERRICK R. |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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