| 摘要 |
The invention relates to a method and an apparatus for reducing memory resources in an integrated circuit. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). The integrated circuit includes a plurality of interconnection lines as well as a first type function block capable of being programmed to operate in a first plurality of modes. The first type function block includes a first plurality of function block Input/Output (I/O) lines. The integrated circuitry also includes a second type function block capable of being programmed to operate in a second plurality of modes. The second type function block includes a second plurality of function block Input/Output (I/O) lines. The integrated circuit includes a shared programmable interface array device operatively connected to the first and second type function blocks. The shared programmable interface array device programmably interconnects the interconnection lines to the function block I/O lines of the first and second type function blocks.
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