DEFECTIVE CELL SCREEN CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE HAVING LATCH STRUCTURE

摘要

PURPOSE: A defective cell screen circuit in semiconductor memory device having latch structure is provided to screen a weak defect affecting a reliability through cell internal power separation in SRAM. CONSTITUTION: The first and second pass transistors(Q1, Q2) have their gates connected to a word line. One side of an active region of the first pass transistor is connected to a bit line(BL), and the other side thereof is connected to the first pull-down transistor(Q3). One side of an active region of the second pass transistor is connected to a complement bit line(BLB), and the other side thereof is connected to the second pull-down transistor(Q4). The first pass and pull-down transistors(Q1, Q3) share a common node(N1), and the second pass and pull-down transistors(Q2, Q4) share a common node(N2). A load resistor(R1) and a gate of the second pull-down transistor(Q4) are connected to the common node(N1). A load resistor(R2) and a gate of the first pull-down transistor(Q4) are connected to the common node(N2). The resistor(R1) is connected to the first power, and the load resistor(R2) is connected to the second power. The first power is different from the second power.