发明名称 METHOD AND DEVICE FOR VERIFYING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten the time required for verification by suppressing the number of test vectors. SOLUTION: Every time when a new test vector is generated and added to a test vector buffer 106 by a test vector generating/adding means 112, a test vector score calculating means 114 calculates a score showing the performance of the test vector. A score increase deciding means 4 compares the calculated score with a score before test vector addition and when the score is not sufficiently increased, an additional test vector abandoning means 6 is started to delete the added test vector from the test vector buffer 106. Only the test vector effective for performing the verification therefore is adopted and the total number of test vectors can be reduced.
申请公布号 JP2002041596(A) 申请公布日期 2002.02.08
申请号 JP20000229352 申请日期 2000.07.28
申请人 SONY CORP 发明人 TERAJIMA MAKOTO
分类号 G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/28
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