发明名称 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To suppress a rise in a via hole resistance by securing an enough contact area between a surface of a second barrier metal layer 13 and a bottom face of a via hole 20. SOLUTION: In forming the via hole 20, the etch selectivity of a first and a third interlayer films 14, 17 with respect to a second interlayer film 16 is made faster. In addition, the film quality of the second interlayer film 16 is different from that of the first and the third interlayer films 14, 17.
申请公布号 JP2002009147(A) 申请公布日期 2002.01.11
申请号 JP20000187868 申请日期 2000.06.22
申请人 TOSHIBA CORP 发明人 YAMAZAKI HIROYUKI
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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